In systems that utilize non-uniform memory access or the like, memory access time depends on the memory location relative to a processor. As caches have grown larger, this non-uniform access time, which typically previously referred to memory, will also apply to on-chip cache. For instance, under NUCA (non-uniform cache architecture) a particular core on a processor can access cache lines nearer to it faster than cache lines stored further away. Different cores on the a given chip will have different cache lines they are close to and different ones that are further away. Such systems introduce uncertainty into the time that it takes to fetch a cache line. This behavior is undesirable for several reasons. For one, some applications are important or have high priority. Those applications should be able to have their cache lines stored in the closer part of the cache that takes fewer cycles to access. For another, some applications need predictable performance. For example, it may be better for a real-time application to have a predictable cycle time such as 5 cycles for all of its cache accesses than to have a variable cycle times such as 1 cycle for some, 2 cycles for others, 8 cycles for yet others, etc., even if the average cycle time for all accesses results in less than the predictable 5 cycle time.
Further, in a core with multiple processing elements (PEs), different PEs have different access times to the cache lines. For instance, it may take PE 0 1 cycle to access line X and 5 cycles to access line Y, while for PE 1 line X takes 5 cycles and line Y takes 1 cycle to access. In this scenario, it is preferable to place PE 0's data in line X and PE 1's data in line Y.
A bank generally refers to all lines in a cache that may be accessed in the same number of cycles. Different PEs and cores are likely to have different bank sizes. The current cache technology does not allow control over in which banks data may be stored. In addition, there is no mechanism in the conventional cache techniques to provide feedback to the software or operating systems as to the banks where particular cache lines are stored. An application may not want its data to be scattered throughout the cache such that access times to that data becomes irregular, that is, some accesses become more expensive than others. Rather, it would be desirable to able to specify that for a given thread its data be stored in a particular bank that would take a desired amount of access time, for example, between 10-12 cycles to fetch. Therefore, what is needed is a method and system that enables placing of cache lines in selected banks. It is also desirable to have a method and system that provides information as to which bank locations cache lines are stored.